SH7641 Datasheet, PDF (87/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 2 CPU
Table 2.2 Destination Register in DSP Instructions
Guard Bits Register Bits
Registers
Instructions
39
32 31
16 15
0
A0, A1
DSP
Fixed-point, PSHA,
PMULS
Sign-extended 40-bit result
Integer, PDMSB
Sign-extended 24-bit result Cleared
Logical, PSHL
Cleared
16-bit result Cleared
Data
transfer
MOVS.W
Sign-extended 16-bit data Cleared
MOVS.L
Sign-extended 32-bit data
A0G, A1G Data
transfer
MOVS.W
MOVS.L
Data
Data
No update
No update
X0, X1
Y0, Y1
M0, M1
DSP
Fixed-point, PSHA,
PMULS
Integer, logical,
PDMSB, PSHL
32-bit result
16-bit result Cleared
Data
transfer
MOVX/Y.W, MOVS.W
MOVS.L
16-bit result
32-bit data
Cleared
Rev. 4.00 Sep. 14, 2005 Page 37 of 982
REJ09B0023-0400