SH7641 Datasheet, PDF (674/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 18 Multi-Function Timer Pulse Unit (MTU)
18.6.2 Interrupt Signal Timing
TGF Flag Setting Timing in Case of Compare Match: Figure 18.64 shows the timing for
setting of the TGF flag in TSR on compare match, and TGI interrupt request signal timing.
Pφ
TCNT input
clock
TCNT
N
N+1
TGR
N
Compare
match signal
TGF flag
TGI interrupt
Figure 18.64 TGI Interrupt Timing (Compare Match)
TGF Flag Setting Timing in Case of Input Capture: Figure 18.65 shows the timing for setting
of the TGF flag in TSR on input capture, and TGI interrupt request signal timing.
Pφ
Input capture
signal
TCNT
N
TGR
N
TGF flag
TGI interrupt
Figure 18.65 TGI Interrupt Timing (Input Capture)
Rev. 4.00 Sep. 14, 2005 Page 624 of 982
REJ09B0023-0400