SH7641 Datasheet, PDF (802/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 20 USB Function Module
Initial
Bit
Bit Name Value
2
EP3TR
0
1
EP3TS
0
0
VBUS
0
R/W Description
R/W EP3 Transfer Request
This bit is set if there is no valid transmit data in the
FIFO buffer when an IN token for endpoint 3 is
received from the host. A NACK handshake is
returned to the host until data is written to the FIFO
buffer and packet transmission is enabled.
R/W EP3 Transmit Complete
This bit is set when data is transmitted to the host
from endpoint 3 and an ACK handshake is returned.
R/W UBS Disconnection Detection
This bit is set to 1 when a function is connected to or
disconnected from the USB bus. Use the VBUSCNT
pin of this module to detect connection/disconnection.
20.3.3 USB Interrupt Flag Register 2 (USBIFR2)
Together with USB interrupt flag registers 0 (USBIFR0) and 1 (USBIFR1), USBIFR2 indicates
interrupt status information required by the application. When an interrupt occurs, the
corresponding bit is set to 1 and an interrupt request is sent to the CPU according to the
combination with USB interrupt enable register 2 (USBIER2). Clearing is performed by writing 0
to the bit to be cleared, and 1 to the other bits. However, CFGV is a status bit, and cannot be
cleared. USBIFR2 is initialized to H'20 by a power-on reset.
Initial
Bit
Bit Name Value R/W Description
7

0
R
Reserved
6

0
R
The write value should always be 0.
5

1
R
4

0
R
3
AWAKE
0
R/W Awake Signal Detection
This bit is set to 1 when the resume or bus reset signal
is detected on the USB bus in the suspend state with
USBCTRL/SUSPEND = 1.
2
SUSPS
0
R/W USB Suspend Signal Detection
This bit is set to 1 when the USB suspend signal is
detected with USBCTRL/SUSPEND = 1.
Rev. 4.00 Sep. 14, 2005 Page 752 of 982
REJ09B0023-0400