SH7641 Datasheet, PDF (492/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 13 Direct Memory Access Controller (DMAC)
CKIO
Bus cycle
DREQ
(Rising)
DACK
(Active-high)
CPU
CPU
1st acceptance
Non sensitive period
DMAC
2nd acceptance
Acceptance
start
CKIO
Bus cycle
DREQ
(Overrun 1 at
high level)
DACK
(Active-high)
CPU
CPU
1st acceptance
Non sensitive period
DMAC
2nd acceptance
DMAC
3rd
acceptance
Acceptance
start
Acceptance
start
Figure 13.16 Example of DREQ Input Detection in Burst Mode Level Detection
Figure 13.17 shows the TEND output timing.
CKIO
Bus cycle
DREQ
DMAC
CPU
End of DMA transfer
DMAC
CPU
CPU
DACK
TEND
Figure 13.17 Example of DREQ Input Detection in Burst Mode Level Detection
Rev. 4.00 Sep. 14, 2005 Page 442 of 982
REJ09B0023-0400