SH7641 Datasheet, PDF (118/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 2 CPU
Type
Arithmetic
operation
instructions
Logic
operation
instructions
Shift
instructions
Kinds of
Instruction
21
Op Code
MUL
MULS
MULU
NEG
NEGC
SUB
SUBC
SUBV
6
AND
NOT
OR
TAS
TST
XOR
12
ROTL
ROTR
ROTCL
ROTCR
SHAL
SHAR
SHLL
SHLLn
SHLR
SHLRn
SHAD
SHLD
Function
Number of
Instructions
Double-precision multiplication
34
(32 × 32 bits)
Signed multiplication (16 × 16 bits)
Unsigned multiplication (16 × 16 bits)
Sign inversion
Sign inversion with borrow
Binary subtraction
Binary subtraction with carry
Binary subtraction with underflow
Logical AND
14
Bit inversion
Logical OR
Memory test and bit setting
Logical AND and T bit setting
Exclusive logical OR
1-bit left rotation
16
1-bit right rotation
1-bit left rotation with T bit
1-bit right rotation with T bit
Arithmetic 1-bit left shift
Arithmetic 1-bit right shift
Logical 1-bit left shift
Logical n-bit left shift
Logical 1-bit right shift
Logical n-bit right shift
Arithmetic dynamic shift
Logical dynamic shift
Rev. 4.00 Sep. 14, 2005 Page 68 of 982
REJ09B0023-0400