SH7641 Datasheet, PDF (808/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 20 USB Function Module
20.3.13 USBEP2 Data Register (USBEPDR2)
USBEPDR2 is a 128-byte transmit FIFO buffer for endpoint 2. USBEPDR2 has a dual-buffer
configuration, and has a capacity of twice the maximum packet size. When transmit data is written
to this FIFO buffer and the EP2PKTE bit in the USB trigger register is set, one packet of transmit
data is fixed, and the dual buffer is switched over. Transmit data for this FIFO buffer can be
transferred by DMA (dual address transfer byte by byte).
USBEPDR2 can be initialized by means of the EP2CLR bit in USBFCLR.
Initial
Bit
Bit Name Value
R/W
31 to 0* D31 to D0 Undefined W
Note: * 7 to 0 bits for DMA transfer.
Description
Data register for endpoint 2 transfer
20.3.14 USBEP3 Data Register (USBEPDR3)
USBEPDR3 is an 8-byte transmit FIFO buffer for endpoint 3, holding one packet of transmit data
in endpoint 3 interrupt transfer. Transmit data is fixed by writing one packet of data and setting the
EP3PKTE bit in the USB trigger register. When an ACK handshake is received from the host after
one packet of data has been transmitted normally, the EP3TS bit in the USB interrupt flag register
0 is set.
USBEPDR3 can be initialized by means of the EP3CLR bit in USBFCLR.
Bit
7 to 0
Bit Name
D7 to D0
Initial
Value
R/W
Undefined W
Description
Data register for endpoint 3 transfer
20.3.15 USBEP0o Receive Data Size Register (USBEPSZ0o)
USBEPSZ0o indicates, in bytes, the amount of data received from the host by endpoint 0o.
USBEPSZ0o can be initialized to H'00 by a power-on reset.
Bit
7 to 0
Bit Name

Initial
Value
All 0
R/W Description
R
Number of bytes received by endpoint 0
Rev. 4.00 Sep. 14, 2005 Page 758 of 982
REJ09B0023-0400