SH7641 Datasheet, PDF (1004/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 25 Electrical Characteristics
25.3.8 Peripheral Module Signal Timing
Table 25.9 Peripheral Module Signal Timing
Conditions: V_CCQ = 3.0 V to 3.6 V, V_CC = 1.8 V ± 5%, AV_CC = 3.0 V to 3.6 V,
V_SS = V_SSQ = AV_SS = 0 V, Ta = −40°C to +85°C
Module Item
Symbol Min.
Max.
Unit Figure(s)
SCIF Input clock cycle (synchronous) t
16
Scyc
(asynchronous)
4
Input clock rising time
Input clock falling time
Input clock width
Transmit data delay time
(synchronous)
t_SCKR
t
SCKF
t
SCKW
t
TXD
—
—
0.4
—
—
t
Pcyc
—
t_Pcyc
1.5
t_Pcyc
1.5
t
Pcyc
0.6
t
Scyc
3 t + 15 ns
Pcyc
25.42
25.42
25.42
25.42
25.42
25.43
Receive data setup time
(synchronous)
t_RXS
4 t_Pcyc + 15 —
ns 25.43
Receive data hold time
(synchronous)
t_RXH
100
—
ns 25.43
PORT Output data delay time
t_PORTD
—
100
ns 25.44
Input data setup time
t
100
—
PORTS2
Input data hold time
t
100
—
PORTH2
DMAC DREQ setup time
t
8
DREQ
—
ns 25.45
DREQ hold time
t
8
—
DREQH
DACK, TEND delay time
t_DACD
—
12
25.46
Note: * t_Pcyc indicate Pclock cycle.
SCK
t_SCKW
t_SCKR
t_Scyc
t_SCKF
Figure 25.42 SCK Input Clock Timing
Rev. 4.00 Sep. 14, 2005 Page 954 of 982
REJ09B0023-0400