SH7641 Datasheet, PDF (278/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 10 Interrupt Controller (INTC)
10.3.5 Interrupt Request Register 0 (IRR0)
IRR0 is an 8-bit register that indicates interrupt requests from external input pins IRQ7 to IRQ0.
This register is initialized to H'00 by a power-on reset or manual reset, but is not initialized in
standby mode.
Initial
Bit
Bit Name Value R/W Description
7
IRQ7R
0
R/W IRQn Interrupt Request
6
IRQ6R
0
R/W Indicates whether there is interrupt request input to the
5
IRQ5R
0
R/W ^{IRQn pin. When edge-detection mode is set for IRQn,}
an interrupt request is cleared by writing 0 to the IRQnR
4
IRQ4R
0
R/W _{bit after reading IRQnR = 1.}
3
IRQ3R
0
R/W _{When level-detection mode is set for IRQn, an interrupt}
2
IRQ2R
0
R/W ^{request is set/cleared by only 1/0 input to the IRQn pin.}
1
IRQ1R
0
R/W
0
IRQ0R
0
R/W ^IRQnR
0: No interrupt request input to IRQn pin
1: Interrupt request input to IRQn pin
n = 0 to 7
Rev. 4.00 Sep. 14, 2005 Page 228 of 982
REJ09B0023-0400