SH7641 Datasheet, PDF (558/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 16 I²C Bus Interface 2 (IIC2)
16.7 Usage Note
Start (retransmission) and stop conditions should be generated after the fall of the ninth clock
pulse has been detected. To detect the fall of the ninth clock pulse, read the SCLO bit in the I²C
Bus Control Register 2 (ICCR2).
When the start (retransmission) or stop condition is attempt to be generated at the specific timing
under the following two conditions, the start or stop condition may not be generated normally.
Under conditions other than following two, generation is performed normally.
• When the load of the SCL bus (load capacitance or pull-up resistance) makes the rising speed
of SCL slower than speeds shown in section 16.6, Bit Synchronous Circuit
• When the low level period between the eighth and ninth clock pulses is extended and bit
synchronous circuit starts operation
Rev. 4.00 Sep. 14, 2005 Page 508 of 982
REJ09B0023-0400