SH7641 Datasheet, PDF (625/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 18 Multi-Function Timer Pulse Unit (MTU)
Example of Cascaded Operation Setting Procedure: Figure 18.18 shows an example of the
setting procedure for cascaded operation.
Cascaded operation
Set cascading
[1]
[1] Set bits TPSC2 to TPSC0 in the channel 1 TCR to
B'1111 to select TCNT_2 overflow/ underflow
counting.
[2] Set the CST bit in TSTR for the upper and lower
channel to 1 to start the count operation.
Start count
[2]
<Cascaded operation>
Figure 18.18 Cascaded Operation Setting Procedure
Examples of Cascaded Operation: Figure 18.19 illustrates the operation when TCNT_2
overflow/underflow counting has been set for TCNT_1 and phase counting mode has been
designated for channel 2.
TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow.
TCLKC
TCLKD
TCNT_2
TCNT_1
FFFD FFFE FFFF 0000 0001
0002
0001 0000 FFFF
0000
0001
0000
Figure 18.19 Example of Cascaded Operation
Rev. 4.00 Sep. 14, 2005 Page 575 of 982
REJ09B0023-0400