SH7641 Datasheet, PDF (123/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 2 CPU
Arithmetic Operation Instructions
Table 2.20 Arithmetic Operation Instructions
Instruction
Instruction Code
ADD
Rm,Rn 0011nnnnmmmm1100
ADD
#imm,Rn 0111nnnniiiiiiii
ADDC
Rm,Rn 0011nnnnmmmm1110
ADDV
Rm,Rn 0011nnnnmmmm1111
CMP/EQ #imm,R0 10001000iiiiiiii
CMP/EQ Rm,Rn 0011nnnnmmmm0000
CMP/HS Rm,Rn 0011nnnnmmmm0010
CMP/GE Rm,Rn 0011nnnnmmmm0011
CMP/HI Rm,Rn 0011nnnnmmmm0110
CMP/GT Rm,Rn 0011nnnnmmmm0111
CMP/PL Rn
0100nnnn00010101
CMP/PZ Rn
0100nnnn00010001
CMP/STR Rm,Rn 0010nnnnmmmm1100
DIV1
Rm,Rn 0011nnnnmmmm0100
DIV0S Rm,Rn 0010nnnnmmmm0111
DIV0U
DMULS.L Rm,Rn
0000000000011001
0011nnnnmmmm1101
Operation
Rn + Rm → Rn
Rn + imm → Rn
Rn + Rm + T → Rn,
Carry → T
Rn + Rm → Rn,
Overflow → T
If R0 = imm, 1 → T
Execution
States
1
1
1
1
1
If Rn = Rm, 1 → T
1
If Rn ≥ Rm with
1
unsigned data, 1 → T
If Rn ≥ Rm with signed data, 1
1→T
If Rn > Rm with
1
unsigned data, 1 → T
If Rn > Rm with signed data, 1
1→T
If Rn > 0, 1 → T
1
If Rn ≥ 0, 1 → T
1
If Rn and Rm have an
1
equivalent byte, 1 → T
Single-step division (Rn/Rm) 1
MSB of Rn → Q,
1
MSB of Rm → M, M ^ Q → T
0 → M/Q/T
1
Signed operation of
Rn × Rm → MACH,
MACL 32 × 32 → 64 bits
2(5) *¹
T Bit
—
—
Carry
Overflow
Comparison
result
Comparison
result
Comparison
result
Comparison
result
Comparison
result
Comparison
result
Comparison
result
Comparison
result
Comparison
result
Calculation
result
Calculation
result
0
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Rev. 4.00 Sep. 14, 2005 Page 73 of 982
REJ09B0023-0400