SH7641 Datasheet, PDF (524/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 16 I²C Bus Interface 2 (IIC2)
SCL
SDA
Output
control
Noise canceler
Output
control
Transmission/
reception
control circuit
ICDRT
ICDRS
Transfer clock
generation
circuit
ICCR1
ICCR2
ICMR
SAR
Noise canceler
ICDRR
NF2CYC
Address
comparator
Bus state
decision circuit
[Legend]
ICCR1 : I²C bus control register 1
ICCR2 : I²C bus control register 2
ICMR : I²C bus mode register
ICSR : I²C bus status register
ICIER : I²C bus interrupt enable register
ICDRT : I²C bus transmit data register
ICDRR : I²C bus receive data register
ICDRS : I²C bus shift register
SAR : Slave address register
NF2CYC: NF2CYC register
Arbitration
decision circuit
ICIER
ICSR
Interrupt
generator
Interrupt
request
Figure 16.1 Block Diagram of I²C Bus Interface 2
Rev. 4.00 Sep. 14, 2005 Page 474 of 982
REJ09B0023-0400