SH7641 Datasheet, PDF (244/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 8 X/Y Memory
8.2 X/Y Memory Access from CPU
The X/Y memory can be accessed by the CPU from spaces P0 and P2. Access from space P0 uses
the I bus, and access from space P2 use the L bus. To use the L bus, one cycle access is performed
unless page conflict occurs. Using the I bus takes more than one cycle access. Figure 8.1 shows
X/Y memory address mapping.
Address A[28:0]
H'04000000
H'05000000
H'0501FFFF
H'055F0000
H'0560FFFF
H'05610000
H'07FFFFFF
Area1, 64 Mbytes
I/O space
16 Mbytes
Reserved
U memory
Reserved
Address A[28:0]
H'05000000
X/Y Memory Spece
Reserved
H'05007000
H'05008000
H'05009000
H'0500FFFF
H'05010000
X memory page0 4 kbytes
X memory page1 4 kbytes
Reserved
Reserved
H'05017000
H'05018000
H'05019000
H'0501FFFF
Y memory page0 4 kbytes
Y memorypage1 4 kbytes
Reserved
Figure 8.1 X/Y Memory Address Mapping
8.3 X/Y Memory Access from DSP
The X/Y memory can be accessed by the DSP from spaces P0 and P2. Methods for accessing
differ according to instructions. Accesses via the X bus/Y bus are always 16-bit, while accesses
via the L bus are either 16-bit or 32-bit. To use the L bus, one cycle access is performed unless
page conflict occurs. Using the I bus takes more than one cycle access.
With X data transfer instructions and Y data transfer instructions, the X/Y memory is accessed via
the X bus or Y bus. These accesses are always 16-bit. In the case of a single data transfer
instruction, the X/Y memory is accessed via the L bus. In this case the access is either 16-bit
or 32-bit.
Accesses via the X bus and Y bus can be specified simultaneously.
Rev. 4.00 Sep. 14, 2005 Page 194 of 982
REJ09B0023-0400