SH7641 Datasheet, PDF (568/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 18 Multi-Function Timer Pulse Unit (MTU)
Table 18.1 MTU Functions
Item
Count clock
General registers
General registers/
buffer registers
I/O pins
Counter clear
function
Compare
match
output
0 output
1 output
Toggle
output
Input capture
function
Synchronous
operation
PWM mode 1
PWM mode 2
Phase counting
mode
Buffer operation
Channel 0 Channel 1 Channel 2 Channel 3 Channel 4
φ/1
φ/4
φ/16
φ/64
TCLKA
TCLKB
TCLKC
TCLKD
φ/1
φ/4
φ/16
φ/64
φ/256
TCLKA
TCLKB
φ/1
φ/4
φ/16
φ/64
φ/1024
TCLKA
TCLKB
TCLKC
φ/1
φ/4
φ/16
φ/64
φ/256
φ/1024
TCLKA
TCLKB
φ/1
φ/4
φ/16
φ/64
φ/256
φ/1024
TCLKA
TCLKB
TGRA_0
TGRB_0
TGRA_1
TGRB_1
TGRA_2
TGRB_2
TGRA_3
TGRB_3
TGRA_4
TGRB_4
TGRC_0


TGRC_3
TGRC_4
TGRD_0
TGRD_3
TGRD_4
TIOC0A
TIOC0B
TIOC0C
TIOC0D
TIOC1A
TIOC1B
TIOC2A
TIOC2B
TIOC3A
TIOC3B
TIOC3C
TIOC3D
TIOC4A
TIOC4B
TIOC4C
TIOC4D
TGR
compare
match or
input capture
TGR
compare
match or
input capture
TGR
compare
match or
input capture
TGR
compare
match or
input capture
TGR compare
match or input
capture
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O



O
O


O


O
O
Rev. 4.00 Sep. 14, 2005 Page 518 of 982
REJ09B0023-0400