SH7641 Datasheet, PDF (411/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 12 Bus State Controller (BSC)
CKIO
A25 to A0
A12/A11*¹
CSn
RASL, RASU
CASL, CASU
RD/WR
DQMxx
D31 to D0
BS
DACKn*²
Td1
Td2
Td3
Td4
Tp
Tpw
Tr
Tc1
Tc2
Tc3
Tc4
Tde
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 12.25 Burst Read Timing
(Bank Active, Different Row Addresses in the Same Bank, CAS Latency 1)
Rev. 4.00 Sep. 14, 2005 Page 361 of 982
REJ09B0023-0400