SH7641 Datasheet, PDF (683/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 18 Multi-Function Timer Pulse Unit (MTU)
18.7.9 Conflict between TGR Write and Input Capture
If an input capture signal is generated in the T2 state of a TGR write cycle, the input capture
operation takes precedence and the write to TGR is not performed.
Figure 18.77 shows the timing in this case.
Pφ
Address
TGR write cycle
T1
T2
TGR address
Write signal
Input capture
signal
TCNT
M
TGR
M
Figure 18.77 Conflict between TGR Write and Input Capture
Rev. 4.00 Sep. 14, 2005 Page 633 of 982
REJ09B0023-0400