SH7641 Datasheet, PDF (141/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 2 CPU
Instruction
Instruction Code
DCF PSHA Sx,Sy,Dz 111110**********
10010011xxyyzzzz
PSHL Sx,Sy,Dz 111110**********
10000001xxyyzzzz
DCT PSHL Sx,Sy,Dz 111110**********
10000010xxyyzzzz
DCF PSHL Sx,Sy,Dz 111110**********
10000011xxyyzzzz
PCOPY Sx,Dz
PCOPY Sy,Dz
DCT PCOPY Sx,Dz
DCT PCOPY Sy,Dz
DCF PCOPY Sx,Dz
DCF PCOPY Sy,Dz
111110**********
11011001xx00zzzz
111110**********
1111100100yyzzzz
111110**********
11011010xx00zzzz
111110**********
1111101000yyzzzz
111110**********
11011011xx00zzzz
111110**********
1111101100yyzzzz
Operation
Execution
States DC
If DC = 0 & Sy > = 0,
1

Sx << Sy → Dz (arithmetic
shift)
If DC = 0 & Sy < 0,
Sx >> Sy → Dz
If DC = 1, nop
If Sy > = 0, Sx << Sy → Dz 1
*
(logical shift)
If Sy < 0, Sx >> Sy → Dz
If DC = 1 & Sy > = 0,
1

Sx << Sy → Dz (logical shift)
If DC = 1 & Sy < 0,
Sx >> Sy → Dz
If DC = 0, nop
If DC = 0 & Sy > = 0,
1

Sx << Sy → Dz (logical shift)
If DC = 0 & Sy < 0,
Sx >> Sy → Dz
If DC = 1, nop
Sx → Dz
1
*
Sy → Dz
1
*
If DC = 1, Sx → Dz
1

If DC = 0, nop
If DC = 1, Sy → Dz
1

If DC = 0, nop
If DC = 0, Sx → Dz
1

If DC = 1, nop
If DC = 0, Sy → Dz
1

If DC = 1, nop
Rev. 4.00 Sep. 14, 2005 Page 91 of 982
REJ09B0023-0400