SH7641 Datasheet, PDF (986/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 25 Electrical Characteristics
CKIO
A25 to A0
Tr
Trw
Tc1
Tcw
t_AD1
Row address
t_AD1
Column address
Td1
Tde
Tap
t_AD1
A12/A11*¹
CSn
RD/WR
RASU/L
CASU/L
DQMxx
t_AD1
t_CSD1
t_AD1
t_AD1
ReadA
command
t_RWD1
t_RASD1
t_RASD1
t_CASD1
t_CASD1
t_DQMD1
D31 to D0
BS
t_BSD
t_BSD
t_CSD1
t_RWD1
t_DQMD1
t_RDS2 t_RDH2
CKE
DACKn*²
t_DACD
(High)
t_DACD
Note: 1. An address pin to be connected to pin A10 of SDRAM.
2. Waveform for DACKn when active low is selected.
Figure 25.24 Synchronous DRAM Single Read Bus Cycle
(Auto Precharge, CAS Latency 2, WTRCD = 1 Cycle, WTRP = 1 Cycle)
Rev. 4.00 Sep. 14, 2005 Page 936 of 982
REJ09B0023-0400