SH7641 Datasheet, PDF (677/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 18 Multi-Function Timer Pulse Unit (MTU)
18.7 Usage Notes
18.7.1 Module Standby Mode Setting
MTU operation can be disabled or enabled using the module standby register.
18.7.2 Input Clock Restrictions
The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at
least 2.5 states in the case of both-edge detection. The TPU will not operate properly at narrower
pulse widths.
In phase counting mode, the phase difference and overlap between the two input clocks must be at
least 1.5 states, and the pulse width must be at least 2.5 states. Figure 18.70 shows the input clock
conditions in phase counting mode.
TCLKA
(TCLKC)
TCLKB
(TCLKD)
Overlap
Phase
Phase
differ-
differ-
ence Overlap ence
Pulse width
Pulse width
Pulse width
Pulse width
Notes: Phase difference and overlap : 1.5 states or more
Pulse width
: 2.5 states or more
Figure 18.70 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
Rev. 4.00 Sep. 14, 2005 Page 627 of 982
REJ09B0023-0400