SH7641 Datasheet, PDF(735/1036 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

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SH7641 Datasheet, PDF (735/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

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Section 19 Serial Communication Interface with FIFO (SCIF)

Section 19 Serial Communication Interface with FIFO

(SCIF)

19.1 Overview

This LSI has a three-channel serial communication interface with FIFO (SCIF) that supports both

asynchronous and clock synchronous serial communication. It also has 16-stage FIFO registers for

both transmission and reception independently for each channel that enable this LSI to perform

efficient high-speed continuous communication.

19.1.1 Features

â¢ Asynchronous serial communication:

ï£§ Serial data communication is performed by start-stop in character units. The SCIF can

communicate with a universal asynchronous receiver/transmitter (UART), an asynchronous

communication interface adapter (ACIA), or any other communications chip that employs

a standard asynchronous serial system. There are eight selectable serial data

communication formats.

ï£§ Data length: 7 or 8 bits

ï£§ Stop bit length: 1 or 2 bits

ï£§ Parity: Even, odd, or none

ï£§ Receive error detection: Parity, framing, and overrun errors

ï£§ Break detection: Break is detected when a framing error is followed by at least one frame at

the space 0 level (low level). It is also detected by reading the RxD level directly from the

port data register when a framing error occurs.

â¢ Synchronous mode:

ï£§ Serial data communication is synchronized with a clock signal. The SCIF can communicate

with other chips having a synchronous communication function. There is one serial data

communication format.

ï£§ Data length: 8 bits

ï£§ Receive error detection: Overrun errors

â¢ Full duplex communication: The transmitting and receiving sections are independent, so the

SCIF can transmit and receive simultaneously. Both sections use 16-stage FIFO buffering, so

high-speed continuous data transfer is possible in both the transmit and receive directions.

â¢ On-chip baud rate generator with selectable bit rates

Rev. 4.00 Sep. 14, 2005 Page 685 of 982

REJ09B0023-0400

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