SH7641 Datasheet, PDF (559/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 17 Compare Match Timer (CMT)
Section 17 Compare Match Timer (CMT)
This LSI has an on-chip compare match timer (CMT) consisting of a two-channel 16-bit timer.
The CMT has a16-bit counter, and can generate interrupts at set intervals.
17.1 Features
CMT has the following features.
• Selection of four counter input clocks
 Any of four internal clocks (Pφ/4, Pφ/8, Pφ/16, and Pφ/64) can be selected independently
for each channel.
• Selection of DMA transfer request or interrupt request generation on compare match
• When not in use, CMT can be stopped by halting its clock supply to reduce power
consumption.
Figure 17.1 shows a block diagram of CMT.
Pφ/4 Pφ/8 Pφ/16 Pφ/64
Control circuit
Clock selection
Pφ/4 Pφ/8 Pφ/16 Pφ/64
Control circuit
Clock selection
Channel 0
Module bus
CMT
[Legend]
CMSTR: Compare match timer start register
CMCSR: Compare match timer control/status register
CMCOR: Compare match timer constant register
CMCNT: Compare match counter
Channel 1
Bus
interface
Internal bus
Figure 17.1 Block Diagram of Compare Match Timer
Rev. 4.00 Sep. 14, 2005 Page 509 of 982
REJ09B0023-0400