SH7641 Datasheet, PDF (622/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 18 Multi-Function Timer Pulse Unit (MTU)
• When TGR is an input capture register
When input capture occurs, the value in TCNT is transferred to TGR and the value previously
held in the timer general register is transferred to the buffer register.
This operation is illustrated in figure 18.14.
Input capture
signal
Buffer
register
Timer general
register
TCNT
Figure 18.14 Input Capture Buffer Operation
Example of Buffer Operation Setting Procedure: Figure 18.15 shows an example of the buffer
operation setting procedure.
Buffer operation
Select TGR function
[1]
Set buffer operation
[2]
[1] Designate TGR as an input capture register or output
compare register by means of TIOR.
[2] Designate TGR for buffer operation with bits BFA and
BFB in TMDR.
[3] Set the CST bit in TSTR to 1 start the count
operation.
Start count
[3]
<Buffer operation>
Figure 18.15 Example of Buffer Operation Setting Procedure
Rev. 4.00 Sep. 14, 2005 Page 572 of 982
REJ09B0023-0400