SH7641 Datasheet, PDF (743/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 19 Serial Communication Interface with FIFO (SCIF)
Initial
Bit
Bit Name value R/W Description
4
O/E
0
R/W Parity mode
Selects even or odd parity when parity bits are added
and checked. The O/E setting is used only in
asynchronous mode and only when the parity enable bit
(PE) is set to 1 to enable parity addition and checking.
The O/E setting is ignored in synchronous mode, or in
asynchronous mode when parity addition and checking
is disabled.
0: Even parity*¹
1: Odd parity*²
Notes: 1. If even parity is selected, the parity bit is
added to transmit data to make an even
number of 1s in the transmitted character and
parity bit combined. Receive data is checked
to see if it has an even number of 1s in the
received character and parity bit combined.
2. If odd parity is selected, the parity bit is added
to transmit data to make an odd number of 1s
in the transmitted character and parity bit
combined. Receive data is checked to see if it
has an odd number of 1s in the received
character and parity bit combined.
3
STOP
0
R/W Stop Bit Length
Selects one or two bits as the stop bit length in
asynchronous mode. This setting is used only in
asynchronous mode. It is ignored in synchronous mode
because no stop bits are added.
When receiving, only the first stop bit is checked,
regardless of the STOP bit setting. If the second stop
bit is 1, it is treated as a stop bit, but if the second stop
bit is 0, it is treated as the start bit of the next incoming
character.
0: One stop bit
When transmitting, a single 1-bit is added at the end
of each transmitted character.
1: Two stop bits
When transmitting, two 1 bits are added at the end of
each transmitted character.
Rev. 4.00 Sep. 14, 2005 Page 693 of 982
REJ09B0023-0400