SH7641 Datasheet, PDF (970/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 25 Electrical Characteristics
25.3.2 Control Signal Timing
Table 25.7 Control Signal Timing
Conditions: V_CCQ = 3.0 V to 3.6 V, V_CC = 1.8 V ±5%, AV_CC = 2.7 V to 3.6 V, V_SSQ = V_SS =
AV_SS = 0 V, Ta = −40°C to +85°C
Bφ = 50 MHz*²
Item
Symbol Min.
Max.
Unit Figure(s)
RESETP pulse width
RESETP setup time*¹
t_RESPW
20*²
—
t_RESPS
22
—
Bcyc*⁴ 25.5, 25.6, 25.9, and
ns
25.10
RESETP hold time
t_RESPH
2
—
ns
RESETM pulse width
t_RESMW
12*³
—
Bcyc*⁴
RESETM setup time
t_RESMS
22
—
ns
RESETM hold time
t_RESMH
12
—
ns
BREQ setup time
t_BREQS
1/2t_cyc + 10 —
ns
25.11
BREQ hold time
t_BREQH
1/2t_cyc + 10 —
ns
NMI setup time*¹
t_NMIS
30
—
ns
25.10
NMI hold time
t_NMIH
30
—
ns
IRQ7 to IRQ0 setup time*¹
t_IRQS
30
—
ns
IRQ7 to IRQ0 hold time
t_IRQH
30
—
ns
BACK delay time
t_BACKD
—
1/2t_cyc + 13 ns
25.11, 25.12
STATUS1, STATUS0 delay time
t_STD
—
100
ns
Bus tri-state delay time 1
t_BOFF1
0
100
ns
Bus tri-state delay time 2
t_BOFF2
0
100
ns
Bus buffer on time 1
t_BON1
0
30
ns
Buss buffer on time 2
t_BON2
0
30
ns
Notes: 1. The RESETP, NMI and IRQ7 to IRQ0 signals are asynchronous signals. When the
setup time is satisfied, change of signal level is detected at the rising edge of the clock.
If not, the detection is delayed until the rising edge of the clock.
2. In standby mode, t_RESP = t_OSC2 (10 ms). When multiplier of the clock is changed, t_REPW = t_PLL1
(100 µs)
3. In standby mode, t_RESP = t_OSC2 (10 ms). When multiplier of the clock is changed, RESETM
must be held low until signals STATUS0 and STATUS1 indicate the reset state (HH).
4. Bcyc indicates external clock cycle time. (B clock cycle)
Rev. 4.00 Sep. 14, 2005 Page 920 of 982
REJ09B0023-0400