SH7641 Datasheet, PDF (236/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 7 Cache
Table 7.7 LRU and Way Replacement (when W2LOCK=0 and W3LOCK=1)
LRU (Bits 5 to 0)
000000, 000001, 000011, 001011, 100000, 100001, 101001, 101011
000100, 000110, 000111, 001111, 010100, 010110, 011110, 011111
110000, 110100, 111000, 111001, 111011, 111100, 111110, 111111
Way to be Replaced
2
1
0
Table 7.8 LRU and Way Replacement (when W2LOCK=1 and W3LOCK=1)
LRU (Bits 5 to 0)
000000, 000001, 000011, 000100, 000110, 000111, 001011, 001111,
010100, 010110, 011110, 011111
100000, 100001, 101001, 101011, 110000, 110100, 111000, 111001,
111011, 111100, 111110, 111111
Way to be Replaced
1
0
7.3 Cache Operation
7.3.1 Searching Cache
If the cache is enabled (CE bit in CCR register is 1), whenever instructions or data in spaces of P0,
P1, and P3 are accessed the cache will be searched to see if the desired instruction or data is in the
cache. Figure 7.2 illustrates the method by which the cache is searched. The cache is a physical
cache of which tag address hold an address.
Entries are selected using bits 11 to 4 of the address used to access memory (virtual address) and
the tag address of that entry is read. The physical address (bits 31 to 12) after translation and the
physical address read from the address section are compared. The address comparison uses all four
ways. When the comparison shows a match and the selected entry is valid (V = 1), a cache hit
occurs. When the comparison does not show a match or the selected entry is not valid (V = 0), a
cache miss occurs. Figure 7.2 shows a hit on way 1.
Rev. 4.00 Sep. 14, 2005 Page 186 of 982
REJ09B0023-0400