SH7641 Datasheet, PDF (684/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 18 Multi-Function Timer Pulse Unit (MTU)
18.7.10 Conflict between Buffer Register Write and Input Capture
If an input capture signal is generated in the T2 state of a buffer register write cycle, the buffer
operation takes precedence and the write to the buffer register is not performed.
Figure 18.78 shows the timing in this case.
Pφ
Address
Write signal
Input capture
signal
TCNT
Buffer register write cycle
T1
T2
Buffer register
address
N
TGR
M
N
Buffer register
M
Figure 18.78 Conflict between Buffer Register Write and Input Capture
18.7.11 TCNT2 Write and Overflow/Underflow Conflict in Cascade Connection
With timer counters TCNT1 and TCNT2 in a cascade connection, when a conflict occurs during
TCNT_1 count (during a TCNT_2 overflow/underflow) in the T₂ state of the TCNT_2 write cycle,
the write to TCNT_2 is conducted, and the TCNT_1 count signal is disabled. At this point, if there
is match with TGRA_1 and the TCNT_1 value, a compare signal is issued. Furthermore, when the
TCNT_1 count clock is selected as the input capture source of channel 0, TGRA_0 to D_0 carry
out the input capture operation. In addition, when the compare match/input capture is selected as
the input capture source of TGRB_1, TGRB_1 carries out input capture operation. The timing is
shown in figure 18.79.
For cascade connections, be sure to synchronize settings for channels 1 and 2 when setting TCNT
clearing.
Rev. 4.00 Sep. 14, 2005 Page 634 of 982
REJ09B0023-0400