SH7641 Datasheet, PDF (493/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 13 Direct Memory Access Controller (DMAC)
To execute a longword access to an 8-bit or 16-bit external device or to execute a word access to
an 8-bit external device, the DACK and TEND outputs are divided for data alignment as shown in
figure 13.18.
CKIO
T₁
T₂ T_aw
T₁
T₂
Read
Address
CSn
RD
D15 to D0
Write
WEn
D15 to D0
DACKn
(Active low)
TENDn
(Active low)
WAIT
Note: TEND is asserted for the last transfer unit of DMA transfers.
If a transfer unit is divided into multiple bus cycles and
if CSn is negated during the bus cycle, TEND is also divided.
Figure 13.18 BSC Ordinary Memory Access
(No Wait, Idle Cycle 1, Longword Access to 16-Bit Device)
Rev. 4.00 Sep. 14, 2005 Page 443 of 982
REJ09B0023-0400