QG5000XSL9TH Datasheet, PDF (99/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.8.6.3
Device:
Function:
Offset:
Version:
16
0
7Ch, 74h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
31:2
1
Attr
RV
RO
0
RO
Default
0h
0
0
Description
Reserved.
2SOCKET: 2 Sockets present on this FSB
Set when Intel 5000P Chipset MCH has seen Ab[22] asserted, indicating there
are more than 1 processors present on this FSB.
2CORE: 2 Cores present
Set when Intel 5000P Chipset MCH has seen Ab[30] asserted, indicating there
is more than 1 core in a processor.
Note: Mixing single core with dual-core processors will be recognized as dual-
core processor on this FSB.
XTPR[7:0] - External Task Priority Register
These registers control redirectable interrupt priority for xAPIC agents connected to the
MCH. Up to four agents on each bus are supported. These agents may be two dual core
processors each with two threads or four single core processors. The xAPIC
architecture provides for lowest priority delivery through interrupt redirection by the
MCH. If the redirectable “hint bit” is set in the xAPIC message, the chipset may redirect
the interrupt to another agent. Redirection of interrupts can be applied to both I/O
interrupts and IPIs.
Each register contains the following fields:
1. Agent priority (Task Priority)
2. APIC enable bit (TPR Enable)
3. Logical APIC ID (LOGID)
4. Processor physical APIC ID (PHYSID)
The XTPR registers are modified by a front side bus xTPR_Update transaction. In
addition, the XTPR registers can be modified by software.
Table 3-31. XTPR Index
Index
3
2
1
0
Value
0 for FSB0, 1 for FSB1
Ab[29]
Ab[30] OR Ab[22]
Ab[21]
These registers are used for lowest priority delivery through interrupt redirection by the
chipset.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
99