QG5000XSL9TH Datasheet, PDF (38/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Signal Description
2.10.2
Reset Timing Requirements
Table 2-3 specifies the timings drawn in Figure 2-2, Figure 2-3, Figure 2-4, and
Figure 2-5. Nominal clock frequencies are described. Specifications still hold for derated
clock frequencies.
Table 2-3. Power Up and Hard Reset Timings
Timing
Description
Min
Max
Comments
T1
Power and master clocks stable to
PWRGOOD signal assertion
2ms
3GIO PLL specification
T2 PWRGOOD de-assertion to straps active
40ns
T3 PWRGOOD de-assertion
80ns
Minimum PWRGOOD de-assertion
time while power and platform
clocks are stable.
T4 POC after RESET# assertion delay
1 BUSCLK
T5
Platform reset de-assertion to platform
reset assertion
50 BUSCLK’s
Minimum re-trigger time on
RESETI# de-assertion.
T7 PWRGOOD assertion to POC active
2 BUSCLK’s
POC turn-on delay after strap
disable
T8 PWRGOOD assertion to straps inactive
12ns
18ns
Strap Hold Time
T9
RESETI# signal assertion during PWRGOOD
/ PWROK signal assertion
1ms
This delay can be provided by the
ICH6 or by system logic
T10
RESET# assertion during processor
PWRGOOD assertion
1ms
10ms
Processor EMTS specification.
T11
RESETI# signal de-assertion to processor
RESET# signal de-assertion
480us¹
Note: This is a special Dual-Core
Intel Xeon 5100 series requirement
to have a longer POC assertion
setup time on the FSB and the
Intel® 5000P chipset has added a
fix in B0 RTL to increase this time
period from 160us to 480us.
T12
RESETI# signal de-assertion to completion
of PCI-Express initialization sequence
1,250,000
PECLK’s
PCI-Express clock is 100MHz
T13 Array Initialization duration
200 cycles
T14 POC hold time after RESET# de-assertion 2 BUSCLK’s
19 BUSCLK’s
Processor EMTS specification
T15
Initiation of DMI reset sequence to
processor RESET# signal de-assertion
10,000 PECLK’s
+ T17
ICH6 specification
T16 RESETI# re-trigger delay
T5 + T9
T17 CPU_RESET_DONE capture timer
2,000 BUSCLK’s
Notes:
1. In the Intel^® 5000P chipset B0 RTL, the T11 duration is implemented through a counter with max value of 162,000 core clocks.
For 333 Mhz, this gives a period of 486 us for the POC setup time while @266 Mhz, the period is 607.5 us.
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Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet