QG5000XSL9TH Datasheet, PDF (255/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.10.2 PCISTS: PCI Status Register
Device:
Function:
Offset:
Version:
8
0
06h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
15
14
Attr Default
Description
RWC 0
RWC 0
DPE: Detected Parity Error
This bit is set when the DMA engine device receives an uncorrectable data error or
Address/Control parity errors regardless of the Parity Error Enable bit (PERRE). This
applies only to parity errors that target the DMA engine device (inbound/outbound
direction). The detected parity error maps to B1, F6, M2 and M4 (uncorrectable data
error from FSB, Memory or internal sources). The DMA engine also records the data
parity error in bit[6] (Cdata_par_err)of the CHANERR register.
SSE: Signalled System Error
13
RO
0
12
RWC 0
11
RWC 0
10:9 RO
00
8
RWC 0
7
RO
0
6
RV
0
5
RO
0
4
RO
1
3
RO
0
2:0
RV
000
1: The DMA engine device reported internal FATAL/NON FATAL errors (DMA0-15)
through the ERR[2:0] pins with SERRE bit enabled. Software clears this bit by
writing a ‘1’ to it.
0: No internal DMA engine device port errors are signaled.
RMA: Received Master Abort Status
This field is hardwired to 0 as there is no Master Abort for the DMA operations
RTA: Received Target Abort Status
This field is hardwired to 0 as there is no Target Abort for the DMA operations
STA: Signalled Target Abort Status:
This field is hardwired to 0
DEVSELT: DEVSEL# Timing:
This bit does not apply to the DMA Engine Device.
MDIERR: Master Data Integrity Error
This bit is set by the DMA engine device if the Parity Error Enable bit (PERRE) is
set and it receives error B1, F2, F6, M2 and M4 (uncorrectable data error or
Address/Control parity errors or an internal failure). If the PERRRSP bit in the
Section 3.10.1 is cleared, this bit is never set.
FB2B: Fast Back-to-Back Capable
Not applicable to DMA Engine. Hardwired to 0.
Reserved
66MHZCAP: 66MHz capable.
Not applicable to DMA Engine. Hardwired to 0.
CAPL: Capability List Implemented:
This bit indicated that the DMA Engine device implements a PCI Capability list. See
CAPPTR at offset 34h
INTxST: INTx State
This bit is set by the hardware when the DMA engine device issues a legacy INTx
(pending) and is reset when the Intx is deasserted.
The intx status bit should be deasserted when all the relevant
status bits/events viz DMA errors/completions that require
legacy interrupts are cleared by software.
Reserved
The PCI Status register follows a subset of the PCI Local Bus Specification, Revision 2.3
specification. This register maintains compatibility with PCI configuration space. Since
this register is part of the standard PCI header, there is a PCISTS register per PCI
function.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
255