QG5000XSL9TH Datasheet, PDF (404/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

6.2
Testability
a single pin (that is, one Boundary-Scan Register Cell after the
differential receiver).
• Internal Signals which control the direction of I/O pins shall also have associated
Boundary- Scan Register Cells.
• Each Output pin (with the exception of TDO) shall be able to be driven to a tristate
condition for HIGHZ test.
Extended Debug Port (XDP)
The Extended Debug Port is covered in the XDP Design Guide.
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Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet