QG5000XSL9TH Datasheet, PDF (140/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
0, 2-3
0
70h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
70h
Intel 5000Z Chipset
4-7
0
70h
Intel 5000P Chipset
Bit
31:28
27:26
Attr
RV
RO
25:18 RO
17:15 RV
14
RO
13
RO
12
RO
11:9 RO
Default
0h
0h
00h
0h
0
0
0
111
Description
Reserved.
CSPLS: Captured Slot Power Limit Scale
Specifies the scale used for the Captured Slot Power Limit Value. It does not
apply to Intel 5000P Chipset MCH as it is a Root complex.
Hardwired to 0h.
CSPLV: Captured Slot Power Limit Value
This field specifies upper limit on power supplied by a slot in an upstream port.
It does not apply to Intel 5000P Chipset MCH as it is a Root complex.
Hardwired to 00h.
Reserved
PIPD: Power Indicator Present on Device
This bit when set indicates that a Power Indicator is implemented.
0: PIPD is disabled in Intel 5000P Chipset MCH
1: Reserved
AIPD: Attention Indicator Present
This bit when set indicates that an Attention Indicator is implemented.
0: AIPD is disabled in Intel 5000P Chipset MCH
1: Reserved
ABPD: Attention Button Present
This bit when set indicates that an Attention Button is implemented.
0: ABPD is disabled in Intel 5000P Chipset MCH
1: Reserved
EPL1AL: Endpoint L1 Acceptable Latency
This field indicates the acceptable latency that an Endpoint can withstand due
to the transition from L1 state to the L0 state.
000: Less than 1µs
001: 1 µs to less than 2 µs
010: 2 µs to less than 4 µs
011: 4 µs to less than 8 µs
100: 8 µs to less than 16 µs
101: 16 µs to less than 32 µs
110: 32 µs to 64 µs
111: More than 64 µs
The Intel 5000P Chipset MCH does not support EndpointL1 acceptable latency
and is set to the maximum value for safety.
140
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet