QG5000XSL9TH Datasheet, PDF (181/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
2-3
0
168h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
168h
Intel 5000Z Chipset
Device:
Function:
Offset:
Version:
4-7
0
168h
Intel 5000P Chipset
Bit
31:1
0
Attr
RV
RWCST
Default
0h
0
Description
Reserved
First_FAT_VPP_Err: VPP Error for PCI Express port
Records the occurrence of the first VPP error if this bit is not set prior.
Software clears this when the error has been serviced.
3.8.12.29 PEX_UNIT_NERR[7:2] - PCI Express Next Unit Error Register
This register records the occurrence of subsequent unit errors that are specific to this
PCI Express port caused by external activities. For example, VPP error due to a
malfunctioning port on the SMBUS that did not receive acknowledge due to a PCI
Express hot-plug event. The next unit errors are sent to the Coherency Engine
where the errors are further recorded and appropriate interrupts are generated through
ERR pins.
.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
2-3
0
16Ch
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
16Ch
Intel 5000Z Chipset
Device:
Function:
Offset:
Version:
4-7
0
16Ch
Intel 5000P Chipset
Bit
31:1
0
Attr
RV
RWCST
Default
0h
0
Description
Reserved
Next_FAT_VPP_Err: VPP Error for PCI Express port
Records the occurrence of subsequent VPP errors after the
PEX_UNIT_FERR.First_FAT_VP_ERR is set.
Software clears this when the error has been serviced.
3.8.12.30 PEX_SSERR[7:2,0]: PCI Express Stop and Scream Error Register
This register records the occurrence of stop and scream error due to data poisoning.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
181