QG5000XSL9TH Datasheet, PDF (344/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Functional Description
management event, it will clear the PEXRTSTS.PMESTATUS bit (by writing 1), at
which point the Intel 5000X chipset MCH can send Deassert_PMEGPE to ESI
port.
The following table summarizes the different types of chipset generated interrupts that
were discussed. Although the interrupt and SW mechanism is flexible and can be
changed depending on how the system is hooked up, for reference this table also
describes what SW mechanism is expected to be used.
Table 5-14. Chipset Generated Interrupts
Source
Signalling mechanism
Intel 5000X Chipset MCH Expected SW
signal method
mechanism
Chipset Error
Intel 5000X chipset MCH
registers
ERR[2:0], MCERR, Intel
631xESB/632xESB I/O
Controller Hub Reset
PCI Express Error
PCI Express ERR_COR/UNC/FATAL ERR[2:0], MCERR, Intel
message
631xESB/632xESB I/O
Controller Hub Reset
PCI Express HP (PresDet
chg, Attn button, and so
forth.)
Intel 5000X chipset MCH
registers
For card-these registers are set
via the VPP/SM bus interface.
MSI or Assert_intx,
Deassert_intx, or
Assert_HPGPE,
Deassert_HPGPE
For module- these registers are
set by inband Hot-Plug messages.
PCI Express HP from
MSI
downstream device
MSI interrupt (processor
bus)
PCI Express HP from
downstream device
(non-native, Intel part)
PCI Express Assert/Deassert GPE Assert_GPE, Deassert_GPE
to ESI
PCI Express HP from
downstream device
(non-native, non-Intel
part)
Sideband signals directly to Intel N/A
631xESB/632xESB I/O Controller
Hub
Downstream PCI Hot-
Plug
PCI Express Assert/Deassert GPE Assert_GPE, Deassert_GPE
to ESI
Power Management
Event (PME)
PCI Express PM_PME message
Assert_PMEGPE,
Deassert_PMEGPE to ESI
Any
Any
SCI->ACPI or
MSI
MSI
SCI->ACPI
SCI->ACPI
SCI->ACPI
SCI->ACPI
5.9.1
Intel 5000X Chipset Generation of MSIs
The Intel 5000X chipset MCH generates MSIs on behalf of PCI Express Hot-Plug events
if Intel 5000P Chipset MCH.MSICTRL.MSIEN is set. Refer to Figure 5-15. The Intel
5000X chipset MCH will interpret PCI Express Hot-Plug events and generate an MSI
interrupt based on Intel 5000P Chipset MCH.MSIAR and Intel 5000P Chipset
MCH.MSIDR registers. When the Intel 5000X chipset MCH detects any PCI Express
Hot-Plug event, it will generate an interrupt transaction to both processor buses. The
address will be the value in Intel 5000P Chipset MCH.MSIAR. The data value will be the
value in MSIDR.
Internal to the Intel 5000X chipset MCH, the MSI can be considered an inbound write
to address MSIAR with data value of MSIDR, and can be handled the same as other
inbound writes that are MSIs or APIC interrupts.
5.9.1.1
MSI Ordering in Intel 5000X Chipset MCH
Ordering issues on internally generated MSIs could manifest in the Intel 5000X chipset
MCH if software/device drivers rely on certain usage models, for example, interrupt
rebalancing, Hot-Plug to flush them. The producer-consumer violation may happen, if a
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Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet