QG5000XSL9TH Datasheet, PDF (313/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Functional Description
5.3.3.3
5.3.3.4
When operating in mirrored mode FB-DIMM Branch 0 (Channels 0/1) and Branch 1
(Channels 2/3) contain replicate copies of data (are mirrored images). Since Branch 1
contains a replicate copy of Branch 0’s data, the maximum addressable memory is
reduced to 32 GB.
Mirrored mode must be selected at configuration time by enabling mirrored operation.
The general flows for mirroring are as follows:
• The same Write (in the non-failed case) is issued to both branches in the same
cycle (which is complete when both branches acknowledge).
• Different Reads (in the non-failed case) are issued to each branch in the same
cycle. Read returns from Branch 1 are delayed two cycles from read returns from
Branch 0.
• Corrected data will be forwarded to the requester.
• Uncorrectable errors will be retried from the other image. If the other image is off-
line, uncorrectable errors will be retried from the same image.
• Software can temporarily degrade operation to one memory branch and then
resume operation with both memory branches.
• To recover from a failed DIMM:
— DIMM failure is detected
— The defective branch is shut down
— The system is gracefully shut down by operator and the defective DIMM is
replaced
— The system is repowered up
— Normal processing is restored
Mirrored Mode ECC
When operating in non-mirrored mode the MCH operates the two branches in lock step
(one branch mirroring the contents of the other). In mirrored mode the maximum
address space is reduced to 32GB because the two channels are mirroring each other.
When operating in mirrored mode both channels on a branch are operated in lock step,
referred to as dual-channel mode.
ECC is calculated using the dual-channel method defined in Section 5.3.3.1.1.
Memory Sparing
At configuration time, a DIMM rank is set aside to replace a defective DIMM rank. When
the error rate for a failing DIMM rank reaches a pre-determined threshold, the
SPCPS.LBTHRconfiguration bit will issue an interrupt and initiate a spare copy. While
the copy engine is automatically reading locations from the failing DIMM rank and
writing them to the spare (see Section 3.9.23.4 and Section 3.9.23.5, “Spare Copy
Status & Spare Copy Control”, system reads will be serviced from the failing DIMM
rank, and system writes will be written to both the failing DIMM rank and the spare
DIMM rank. At the completion of the copy, the failing DIMM rank is disabled and the
“spared” DIMM rank will be used in its place. The MCH will change the rank numbers in
the DMIRs from the failing rank to the spare rank. DMIR.LIMIT’s are not updated.
This mechanism requires no software support once it has been enabled by designating
the spare rank through the SPCPC.SPRANK configuration register field and enabling
sparing by setting the SPCPC.SPAREN configuration bit. Hardware will detect the
threshold-initiated fail, accomplish the copy, and off-line the “failed” DIMM rank once
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
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