QG5000XSL9TH Datasheet, PDF (287/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

System Address Map
This region is used to support various processor and system functions. These functions
include I/O APIC control range which is used to communicate with I/O APIC controllers
located on Intel 6700PXH 64 bit PCI Hub and Intel 631xESB/632xESB I/O Controller
Hub devices. The high SMM range is enabled under register control. Transactions
directed to this range are redirected to physical memory located in the compatible
(legacy) SMM space; 0A 0000h - 0B FFFFh. The interrupt range is used to deliver
interrupts. Memory read or write transactions from the processor are illegal.
4.3.7.1
I/O APIC Controller Range
This address range FEC0 0000h to FEC8 FFFF is used to communicate with the IOAPIC
controllers in the Intel^® 6700PXH 64 bit PCI Hub or Intel 631xESB/632xESB I/O
Controller Hub devices.
The APIC ranges are hard coded. Reads and writes to each IOAPIC region should be
sent to the appropriate ESI or PCI Express port as indicated below.
Table 4-4.
I/O APIC Address Mapping
IOAPIC0 (ESI)
IOAPIC1 (PEX2)
IOAPIC2 (PEX3)
IOAPIC3 (PEX4)
IOAPIC4 (PEX5)
IOAPIC5 (PEX6)
IOAPIC6 (PEX7)
Reserved (Intel®
631xESB/632xESB
I/O Controller Hub
for master abort)
FEC0 0000h to FEC7 FFFFh
FEC8 0000h to FEC8 0FFFh
FEC8 1000h to FEC8 1FFFh
FEC8 2000h to FEC8 2FFFh
FEC8 3000h to FEC8 3FFFh
FEC8 4000h to FEC8 4FFFh
FEC8 5000h to FEC8 5FFFh
FEC0 6000h to FEC8 FFFFh
For Hot-Plug I/O APIC support, it is recommended that software use the standard MMIO
range to communicate with the Intel 6700PXH 64 bit PCI Hub. To accomplish this, the
Intel 6700PXH 64 bit PCI Hub.MBAR and/or Intel 6700PXH 64 bit PCI
Hub.XAPIC_BASE_ADDRESS_REG must be programmed within the PCI Express device
MMIO region.
Inbound accesses to this memory range should also be routed to the I/O APIC
controllers. This could happen if software configures MSI devices to send MSIs to an I/
O APIC controller.
4.3.7.2
High SMM Range
If high SMM space is enabled by EXSMRC.H_SMRAME, then requests to the address
range from FEDA 0000h to FEDB FFFFh will be aliased down to the physical address of
A 0000h to B FFFFh. The HIGHSMM space allows cacheable accesses to the compatible
(legacy) SMM space. In this range, the chipset will accept EWBs (BWLs) regardless of
the SMMEM# pin. Also, if there is an implicit write back (HITM with data), the chipset
will update memory with the new data (regardless of the SMMEM# pin). Note that if the
HIGHSMM space is enabled, the aliased SMM space of 0A 0000h - 0B FFFFh will be
disabled.
Note: In order to make cacheable SMM possible, the chipset must accept EWBs (BWLs)
and must absorb IWB (HITM) data regardless of the condition of the SMMEM# pin.
Because of this, care must be used when attempting to cache SMM space. The chipset/
platform cannot protect against processors who attempt to illegally access SMM space
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
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