QG5000XSL9TH Datasheet, PDF (231/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
Each register defines a range. If the Memory (M) address falls in the range defined by
an adjacent pair of DMIR.LIMIT’s, the rank fields in the upper DMIR define the number
and interleave position of ranks’ way participation. Matching addresses participate in
the corresponding ways. The combination of two equal ranks with three unequal ranks
is illegal.
When a DMIR is programmed for a 2-way interleave, RANK0/RANK2 should be with the
same rank number and RANK1/RANK3 should be another rank number.
This register must not be modified while servicing memory requests.
3.9.23.9
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
21
0
A0h, 9Ch, 98h, 94h, 90h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
22
0
A0h, 9Ch, 98h, 94h, 90h
Intel 5000P Chipset
Bit
31:24
23:16
Attr
RV
RW
15:12 RV
11:9 RW
8:6
RW
5:3
RW
2:0
RW
Default
000h
00h
0h
000
000
000
000
Description
Reserved
LIMIT
This field defines the highest address in the range. Memory requests
participate in this DMIR range if LIMIT[i] > M[34:28] >= LIMIT[i-1]. For i = 0,
LIMIT[i-1]=0 (M[35] is considered as zero for the purpose of this comparison).
Reserved
RANK3
Defines which rank participates in WAY3.
RANK2
Defines which rank participates in WAY2.
RANK1
Defines which rank participates in WAY1.
RANK0
Defines which rank participates in WAY0.
FBDICMD[1:0][1:0] - FB-DIMM Initialization Command
These registers define channel behavior during the “Init”, “Recovery Init”, “Reset”, and
“Recovery Reset” hot-plug states. The “AMBID” field for the even-numbered channel
also defines branch behavior during fast reset.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
21
0
47h, 46h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
22
0
47h, 46h
Intel 5000P Chipset
Bit
Attr
Default
Description
7
RW
0
EN: Enable
‘0’ = Drive electrical idle on the channel.
‘1’ = Drive INITPAT on the channel.
This field is not used during fast reset.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
231