QG5000XSL9TH Datasheet, PDF (275/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.11.10 DIO[1:0]SQUELCH_CNT: PCIe Cluster Squelch Count
Device: 4, 0
Function: 0
Offset: 396h
Bit Attr Default
Description
15:12 RV
11 RWST
10 RWST
9:0
RV
1h
1h
0h
164h
Reserved
Dis_Rx_L1L0s_idle: Disable automatic shutoff of receivers during L1.Idle/
L0s.Idle power states
1: Disable automatic shut off of receivers during L1 or L0s idle power state entry.
(default).
0: Enables Rx shut off. This bit when clear forces the hardware to shut off the
Receiver side in BNB during the L0s/L1 power states.
Note: This bit is functional in MCH steppings B3 and newer. Refer to erratum 19
(501621).
DIS_LANE_LANE_DESKEW: Disable Lane to Lane Deskew
1: Lane to lane deskew is disabled. Should be set before Intel IBIST is started and
cleared after Intel IBIST is stopped
0: Normal link operation. i.e Lane to lane deskew is enabled (default)
Reserved
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Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
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