QG5000XSL9TH Datasheet, PDF (36/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Signal Description
2.10 Reset Requirements
2.10.1 Timing Diagrams
2.10.1.1 Power-Up
The power-up sequence is illustrated in Figure 2-2.
Figure 2-2. Power-Up
Power Rails
PWRGOOD
RESETI#
Synchronized RESETI#
processor RESET#
POC
Events Internal power detect
FBD
PCI-Express
PCI-Express Compatibility
BUSCLK
PLL's
T1
T9
T10
T11
T8
T7
Non-FBD Analog
compensation ^Straps
completed
sampled
Straps Fuses
inactive downloaded
Reset
T13
T17
Array Init
Done
Init
T12
initialization
2.10.1.2 Power Good
The PWRGOOD reset sequence is illustrated in Figure 2-3.
Figure 2-3. PWRGOOD
PWRGOOD
RESETI#
Synchronized RESETI#
processor RESET#
POC
Events
FBD
PCI-
PCI-Express ComExpparteibsislity
BUSCLK
PLL's
Sticky Bits
Straps
T2 active
T3
T9
T10
T11
T8
T7
Straps
sampled
Straps Fuses
inactive downloaded
Reset
T13
T17
Array Init
Done
Init
T12
initialization
2.10.1.3
Hard Reset
The Hard Reset sequence is illustrated in Figure 2-4.
T14
T15
Level
full operation
T14
T15
Level
full operation
DMI handshake done
DMI handshake done
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Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet