QG5000XSL9TH Datasheet, PDF (87/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.8.2.8
SMRAMC - System Management RAM Control Register
The SMRAMC register controls how accesses to Compatible and Extended SMRAM
spaces are treated. The Open, Close, and Lock bits function only when
EXSMRC.G_SMRAME bit is set to a 1. Also, the OPEN bit must be reset before the LOCK
bit is set.
Device:
Function:
Offset:
Version:
16
0
61h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
7
RV
6
RWL
5
RW
4
RWL
3
RV
2:0
RO
0
Reserved
0
D_OPEN: SMM Space Open
When D_OPEN=1 and D_LCK=0, the SMM space DRAM is made visible even
when SMM decode is not active. This is intended to help BIOS initialize SMM
space. Software should ensure that D_OPEN=1 and D_CLS=1 are not set at
the same time. This register can be locked by D_LCK.
0
D_CLS: SMM Space Closed
When D_CLS = 1 SMM space DRAM is not accessible to data references, even
if SMM decode is active. Code references may still access SMM space DRAM.
This will allow SMM software to reference through SMM space to update the
display even when SMM is mapped over the VGA range. Software should
ensure that D_OPEN=1 and D_CLS=1 are not set at the same time. Note that
the D_CLS bit only applies to Compatible SMM space.
0
D_LCK: SMM Space Locked
When D_LCK is set to 1 then D_OPEN is reset to 0 and D_LCK, D_OPEN,
C_BASE_SEG, H_SMRAME, G_SMRAME, all LT.MSEG.BASE, all LT.MSEG.SIZE,
ESMMTOP, TSEG_SZ and T_EN become read only. D_LCK can be set to 1 via a
normal configuration space write but can only be cleared by a Full Reset. The
combination of D_LCK and D_OPEN provide convenience with security. The
BIOS can use the D_OPEN function to initialize SMM space and then use
D_LCK to “lock down” SMM space in the future so that no application software
(or BIOS itself) can violate the integrity of SMM space, even if the program
has knowledge of the D_OPEN function.
0
Reserved
010
C_BASE_SEG: Compatible SMM Space Base Segment
This field indicates the location of legacy SMM space. SMM DRAM is not
remapped. It is simply made visible if the conditions are right to access SMM
space, otherwise the access is forwarded to ESI/VGA. Since the MCH supports
only the SMM space between A 0000h and B FFFFh, this field is hardwired to
010.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
87