QG5000XSL9TH Datasheet, PDF (14/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Introduction
Table 1-1.
General Terminology (Sheet 2 of 7)
Terminology
Description
Buffer
Cache Line
CDM
Cfg, Config
Channel
Character
Chipset Core
Coherent
Command
Completion
Core
CRC
Critical Word First
DDR
Deasserted
Deferred Transaction
Delayed Transaction
DFx (DFD, DFM, DFT,
DFV)
DIMM
Double-Sided DIMM
Downstream
DRAM Page (Row)
1. A random access memory structure.
2. The term I/O buffer is also used to describe a low level input receiver and output
driver combination.
The unit of memory that is copied to and individually tracked in a cache. Specifically,
64 bytes of data or instructions aligned on a 64-byte physical address boundary.
Central Data Manager. A custom array within the Intel 5000X chipset that acts as a
temporary repository for system data in flight between the various ports: FSB’s,
FBD’s, ESI, and PCI Express*.
Abbreviation for “Configuration”.
In the MCH a FBD DRAM channel is the set of signals that connects to one set of FBD
DIMMs. The MCH has up to four DRAM channels.
The raw data byte in an encoded system (for example, the 8b value in a 8b/10b
encoding scheme). This is the meaningful quantum of information to be transmitted or
that is received across an encoded transmission path.
The MCH internal base logic.
Transactions that ensure that the processor's view of memory through the cache is
consistent with that obtained through the I/O subsystem.
The distinct phases, cycles, or packets that make up a transaction. Requests and
completions are referred to generically as Commands.
A packet, phase, or cycle used to terminate a transaction on a interface, or within a
component. A Completion will always refer to a preceding request and may or may not
include data and/or other information.
The internal base logic in the Intel 5000X chipset.
Cyclic Redundancy Check; A number derived from, and stored or transmitted with, a
block of data in order to detect corruption. By recalculating the CRC and comparing it
to the value originally transmitted, the receiver can detect some types of transmission
errors.
On the DRAM, Processor, and Memory interfaces, the requestor may specify a
particular word to be delivered first. This is done using address bits of lower
significance than those required to specify the cache line to be accessed. The
remaining data is then returned in a standardized specified order.
Double Data Rate SDRAM. DDR describes the type of DRAMs that transfers two data
items per clock on each pin. This is the only type of DRAM supported by the MCH.
Signal is set to a level that represents logical false.
A processor bus Split Transaction. On the processor bus, the requesting agent
receives a Deferred Response which allows other transactions to occur on the bus.
Later, the response agent completes the original request with a separate Deferred
Reply transaction or by Deferred Phase.
A transaction where the target retries an initial request, but without notification to the
initiator, forwards or services the request on behalf of the initiator and stores the
completion or the result of the request. The original initiator subsequently re-issues
the request and receives the stored completion
DFD=Design for Debug
DFM=Design for Manufacturing
DFT=Design for Testability
DFV=Design for Validation
Dual-in-Line Memory Module. A packaging arrangement of memory devices on a
socketable substrate.
Terminology often used to describe a DIMM that contain two DRAM rows. Generally a
Double-sided DIMM contains two rows, with the exception noted above. This
terminology is not used within this document.
See Terminology entry of “Inbound (IB)/Outbound (OB), AKA Upstream/DownStream,
Northbound/Southbound, Upbound/Downbound”
The DRAM cells selected by the Row Address.
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Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet