QG5000XSL9TH Datasheet, PDF (274/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.11.9
PEX[7:2,0]IBLNS[3:0]: PEX Intel IBIST Lane Status
This register contains the control bits and status information necessary to perate the
Fixed and Open modes of the Intel IBIST logic. The default settings allow the CMM logic
to operate with link width of a PEX port. Only valid PCI Express control characters/
symbols are allowed for Intel IBIST testing.
Device: 3-2, 0
Function: 0
Offset: 393h, 392h, 391h, 390h
Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
Version:
4-5
0
393h, 392h, 391h, 390h
Intel 5000Z Chipset
Device: 4-7
Function: 0
Offset: 393h, 392h, 391h, 390h
Version: Intel 5000P Chipset
Bit
Attr Default
Description
7
RO
6:4
RO
3
RWC
2
RV
1
RWCST
0
RW
ERRPTRTYP: Error Symbol Pointer Type
This bit indicates whether or not the errant symbol pointer was a delay symbol
set. If an Intel IBIST engine is implemented with the MISR compare method
0
then this field is reserved.
0: Errant symbol pointer was a DATA symbol set
1: Errant symbol pointer was a DELAY symbol set
ERRPTR: Error Symbol Pointer
This value indicates which symbol of the 8 possible symbols sent on the lane, as
0h _{a set of characters, failed. The value corresponds to position of the set of 8}
symbols. If an Intel IBIST engine is implemented with the MISR compare
method then this field is reserved.
IBLOOPSTAT: Intel IBIST Loopback State Status:
This bit is set when the Rx received a TS1 with the loopback bit set. Write a logic
0
‘1’ to clear.
0: Intel IBIST did not receive a TS1 with loopback bit set.
1: Intel IBIST received a TS1 with loopback bit set.
0
Reserved.
ERRLNSTAT: Error Lane Status
Error assertion for this lane. Writing a logic ‘1’ will clear this bit. This bit is sticky.
0
0: No error on this lane
1: Error has occurred on this lane
LNSTREN: Lane Start Enable
When the lane is disabled, no electrical transmissions may occur on the Tx
driver and the receiver’s (Rx) Intel IBIST error reporting is suppressed. This
allows the pattern generator and receiver checking logic to function normally if
required for design simplicity. But it forces a quite Tx lane for adjacent lane
1
testing.
0: This lane is disabled from Intel IBIST testing, no Tx transmissions and Rx
error reporting is suppressed.
1: Lane enabled. Allows the port start bit to begin Intel IBIST symbol operations
on this lane.
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Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet