QG5000XSL9TH Datasheet, PDF (299/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Functional Description
5 Functional Description
5.1
5.1.1
This chapter describes each of the MCH interfaces and functional units including the
Dual Independent Bus (DIB), processor Frontside Bus (FSB) interface, the PCI Express
ports, system memory controller, power management, and clocking.
Processor Front Side Buses
The MCH supports two Dual-Core Intel^® Xeon^® 5000 Sequence processors on a 65
nanometer process in a 771-land, FC-LGA4 package. Dual-Core Intel Xeon 5000
Sequence is a fourth generation 32-bit Intel^® Xeon processor supporting Intel^®
Extended Memory 64 Technology (Intel^® EM64T) based on Intel NetBurst^®
microarchitecture.
The MCH supports 1066/1333 MHz FSB which is a quad-pumped bus running off a
266/333 MHz system clock, and a point to point DIB processor system bus interface.
Each processor FSB supports peak address generation rates of 533 Million Addresses/
second. Both FSB data buses are quad pumped 64-bits which allows peak bandwidths
of 8.5 GB/s (1066 MT/s) and 10.5 GB/s (1333 MT/s). The MCH supports 36-bit host
addressing, decoding up to 64 GB of the processor’s memory address space. Host-
initiated I/O cycles are decoded to AGP/PCI, PCI Express, ESI interface or MCH
configuration space. Host-initiated memory cycles are decoded to AGP/PCI, PCI
Express, ESI or system memory.
FSB Overview
The MCH is the only priority agent for two point to point, independent, processor front
side buses (FSB). These two buses are referred to as Dual Independent Buses (DIB).
The MCH maintains coherency across these two buses. The MCH may complete
deferrable transactions with either defer-replies or in-order responses. Intel 5000X
chipset contains an internal Snoop-Filter to remove unnecessary snoops on the remote
FSB, and to be able to complete transactions in-order without deferring for transactions
that do not need to have a remote snoop. Data transactions on the FSBs are optimized
to support 64 byte cache lines.
Each processor FSB contains a 36 bit address bus, a 64 bit data bus, and associated
control signals. The FSB utilizes a split-transaction, deferred reply protocol. The FSB
uses source-synchronous transfer of address and data to improve performance. The
FSB address bus is double pumped (2X) with ADS being sourced every other clock. The
address bus generates a maximum bandwidth of 133 Million Addresses/second (MA/s).
The FSB data bus is quad pumped (4X) and supports peak bandwidths of 8.5 GB/s
(1066 MT/s) and 10.5 GB/s (1333 MT/s). Parity protection is applied to the data bus.
This yields a combined bandwidth of 17 GB/s (1066 MT/s) and 21 GB/s (1333 MT/s) for
both FSBs.
Interrupts are also delivered via the FSB.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
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