QG5000XSL9TH Datasheet, PDF (375/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Functional Description
5.16.4.2
Configuration Register Read Protocol
Configuration reads are accomplished through an SMBus write(s) and later followed by
an SMBus read. The write sequence is used to initialize the Bus Number, Device,
Function, and Register Number for the configuration access. The writing of this
information can be accomplished through any combination of the supported SMBus
write commands (Block, Word or Byte). The Internal Command field for each write
should specify Read DWord.
After all the information is set up, the last write (End bit is set) initiates an internal
configuration read. If the data is not available before the slave interface acknowledges
this last write command (ACK), the slave will “clock stretch” until the data returns to
the SMBus interface unit. If an error occurs during the internal access, the last write
command will receive a NAK. A status field indicates abnormal termination and contains
status information such as target abort, master abort, and time-outs. The status field
encoding is defined in the following table.
Table 5-23. Status Field Encoding for SMBus Reads
Bit
7
6
5
4
3:1
0
Description
Internal Time-out. This bit is set if an SMBus request is not
completed in TBD internally (2ms?)
Reserved
Internal Master Abort
Internal Target Abort
Reserved
Successful
Examples of configuration reads are illustrated below. All of these examples have
Packet Error Code (PEC) enabled. If the master does not support PEC, then bit 4 of the
command would be cleared and there would not be a PEC phase. For the definition of
the diagram conventions below, refer to the SMBus Specification, Revision 2.0. For
SMBus read transactions, the last byte of data (or the PEC byte if enabled) is NAKed by
the master to indicate the end of the transaction. For diagram compactness, “Register
Number[]” is also sometimes referred to as “Reg Number” or “Reg Num”.
Figure 5-37. SMBus Configuration Read (Block Write / Block Read, PEC Enabled)
S 11X0_XXX W A Cmd = 11010010 A Byte Count = 4 A
SMBUS write
S 11X0_XXX W A Cmd = 11010010 A
Sr
11X0_XXX
R A Byte Count = 5 A
Status
A
Bus Number
A Device/Function A Reg Number[7:0] A
Reg Number [15:8] A
PEC
CLOCK
STRETCH
AP
Data[31:24]
A
Data[23:16]
A
SMBUS read
Data[15:8]
A
Data[7:0]
A
PEC
NP
This is an example using word reads. The final data is a byte read.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
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