QG5000XSL9TH Datasheet, PDF (197/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
Table 3-37. Global Activation Throttling as a Function of Global Activation Throttling Limit
(GBLACTM) and Global Throttling Window Mode (GTW_MODE) Register Fields
GBLACT.GBLACTM
Range (0.168)
96
100
128
150
168
Number of Activations
MC.GTW_MODE=0
(16384*1344 window)
6291456
6553600
8388608
9830400
11010048 (100% BW)
MC.GTW_MODE=1
(4*1344 window)
1536
1600
2048
2400
2688 (100% BW)
3.9.3 THRTSTS[1:0] - Thermal Throttling Status Register
Device:
Function:
Offset:
Version:
16
1
6Ah, 68h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit Attr Default
Description
15:9 RV
8
RO
0h Reserved
0h GBLTHRT: Global Activation Throttle¹
This field is set by the Intel 5000P Chipset MCH to indicate the start of the Global
Activation throttling based on the number of activates sampled in the global
window.
If the number of activates in the global window (16384*1344 cycles) exceeds the
number indicated by the GBLACTLM field in this register, then THRTSTS.GBLTHRT
bit is set to enable the Global activation throttling logic.
Global activation throttling logic will remain active until 16 (or 2) global throttling²
windows in a row have gone by without any DIMM exceeding the
GBLACT.GBLACTLM register at which point this register field will be reset.
7:0
RO
0h THRMTHRT: Thermal Throttle Value
This field holds the current activation throttling value based on the Intel 5000P
Chipset MCH/FB-DIMM throttling algorithm.
0: No throttling (unlimited activation)
1: 4 activations per activation window
2: 8 activations per activation window
168: 672 activations per activation window
This field will be set by the Intel 5000P Chipset MCH and the value of this field will
vary between THRTLOW and THRTHI registers based on the throttling.
Notes:
1. The Intel 5000P Chipset MCH will use an internal signal called GBLTHRT* from its combinatorial cluster for
controlling open loop throttling.
2. If MC.GTW_MODE=1, then the debug mode is enabled and the Intel 5000P Chipset MCH will use 2 windows
for global activation logic to be valid.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
197