QG5000XSL9TH Datasheet, PDF (163/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.8.12.4
Device:
Function:
Offset:
Version:
0
0
104h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
11:6
5
4
3:1
0
Attr
RV
RWST
RWCST
RV
RWCST
Default
0h
0
0
0h
0
Description
Reserved
IOErr: Surprise Link Down Error Status
IO0Err: Data Link Protocol Error Status
Reserved
IO3Err:Training Error Status
Note: This field should not be used for obtaining Training error status
due to a recent PCI Express Base Specification, Revision 1.0a
Errata Dec 2003 to remove training error. Hardware behavior is
undefined.
UNCERRMSK[7:2] - Uncorrectable Error Mask
This register masks uncorrectable errors from the UNCERRSTS[2:7] register from being
signaled.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
2-3
0
108h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
108h
Intel 5000Z Chipset
Device:
Function:
Offset:
Version:
4-7
0
108h
Intel 5000P Chipset
Bit
31:21
20
19
18
17
16
15
14
13
12
11:6
5
4
3:1
0
Attr
RV
RWST
RV
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RV
RWST
RWST
RV
RWST
Default
0h
0
0
0
0
0
0
0
0
0
0h
0
0
000
0
Description
Reserved
IO2Msk: Received an Unsupported Request
Reserved
IO9Msk: Malformed TLP Status
IO10Msk: Receiver Buffer Overflow Mask
IO8Msk: Unexpected Completion Mask
IO7Msk: Completer Abort Status
IO6Msk: Completion Time-out Mask
IO5Msk: Flow Control Protocol Error Mask
IO4Msk: Poisoned TLP Mask
Reserved
IO19Msk: Surprise Link Down Error Mask
IO0Msk: Data Link Layer Protocol Error Mask
Reserved
IO3Msk:Training Error Mask
Note: This field should not be used for setting Training error Mask due to
a recent PCI Express Base Specification, Revision 1.0a Errata Dec
2003 to remove training error. Hardware behavior is undefined.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
163