QG5000XSL9TH Datasheet, PDF (105/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.8.8.2
PCISTS[7:2, 0] - Status Register
The PCISTS is a 16-bit status register that reports the occurrence of error conditions
associated with the primary side of the “virtual” PCI-PCI bridge embedded in the
selected PCI Express cluster of the MCH.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
0, 2-3
0
06h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
06h
Intel 5000Z Chipset
4-7
0
06h
Intel 5000P Chipset
Bit
Attr
15
RWC
14
RWC
13
RWC
12
RWC
11
RO
10:9 RO
Default
0
0
0
0
0
0h
Description
DPE: Detected Parity Error
This bit is set when the PCI Express port receives an uncorrectable data error
or Address/Control parity errors regardless of the Parity Error Response
Enable bit (PERRE). This applies only to parity errors that target the PCI
Express port interface (inbound/outbound direction). The detected parity error
maps to B1, F6, M2 and M4 (uncorrectable data error from FSB, Memory or
internal sources) of the Intel 5000P Chipset MCH.
SSE: Signaled System Error
1: The PCI Express port generated internal FATAL/NON FATAL errors (IO0-
IO17) through the ERR[2:0] pins with SERRE bit enabled. Software clears this
bit by writing a ‘1’ to it.
0: No internal PCI Express port errors are signaled.
RMA: Received Master Abort
This bit is set when a requestor (primary side for Type 1 header configuration
space header device) receives a completion with Unsupported Request
Completion Status.
1: Assert this RMA bit when the primary side performs operations for an
unsupported transaction. These apply to inbound configs, I/O accesses, locks,
bogus memory reads and any other request that is master aborted internally.
These are terminated on the PCI Express link with a UR completion status, but
only if a completion is required. Software clears this bit by writing a 1 to it.
PEXDEVSTS.URD is set and UNCERRSTS[20].IO2Err is set in addition.
0: No Master Abort is generated
RTA: Received Target Abort
This bit is set when a requestor (primary side for Type 1 header configuration
space header device) receives a completion with Completer Abort Completion
Status. For example, for supported requests that cannot be completed
because of address decoding problems or other errors. These are terminated
on the PCI Express link with a CA completion status, but only if a completion is
required. Software clears this bit by writing a 1 to it.
STA: Signaled Target Abort
Target Abort does not exist on the primary side of the PCI Express port.
Hardwired to 0.
DEVSELT: DEVSEL# Timing
Not applicable to PCI Express. Hardwired to 0.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
105