QG5000XSL9TH Datasheet, PDF (120/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.8.8.28
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
0, 2-3
0
3Dh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
3Dh
Intel 5000Z Chipset
4-7
0
3Dh
Intel 5000P Chipset
Bit
Attr
Default
Description
7:0 RWO
01h
INTP: Interrupt Pin
This field defines the type of interrupt to generate for the PCI Express port.
001: Generate INTA
010: Generate INTB
011: Generate INTC
100: Generate INTD
Others: Reserved
BIOS/configuration Software has the ability to program this register once
during boot to set up the correct interrupt for the port.
BCTRL[7:2] - Bridge Control Register
This register provides extensions to the PCICMD register that are specific to PCI-PCI
bridges. The BCTRL provides additional control for the secondary interface (that is, PCI
Express) as well as some bits that affect the overall behavior of the “virtual”
PCI-PCI bridge embedded within the MCH, for example, VGA compatible address
range mapping.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
2-3
0
3Eh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
3Eh
Intel 5000Z Chipset
4-7
0
3Eh
Intel 5000P Chipset
Bit
15:12
11
Attr
RV
RO
10
RO
9
RO
Default
0h
0
0
0
Description
Reserved. (by PCI SIG)
DTSS: Discard Timer SERR Status
Not applicable to PCI Express. This bit is hardwired to 0.
DTS: Discard Timer Status
Not applicable to PCI Express. This bit is hardwired to 0.
SDT: Secondary Discard Timer
Not applicable to PCI Express. This bit is hardwired to 0.
120
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet