QG5000XSL9TH Datasheet, PDF (238/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
Device: 22
Function: 0
Offset: 280h, 180h
Bit
Attr Default
Description
24
RW
23
RW
22
RW
21:12 RWST
11:8 ROST
7:6 RWCST
5
RW
4
RW
3
RW
2
RWCST
1
0
0
000h
00h
0
1
1
0
0
RXAUTOINVSWPEN: Auto-inversion sweep enable
This bit enable the inversion shift register to continuously rotate the pattern in
the FIBRXSHFT register. This register enables the inversion pattern to the lane at
the bit position indicated by a logic 1.
0: Disable Auto-inversion
1: Enable Auto-inversion
Intel 5000P Chipset MCHMAP: Southbound to northbound mapping for
loopback testing
This bit indicates which set of lanes are replicated onto the northbound lanes.
0: Lower SB lanes
1: Upper SB lanes
CMMSTR: Compliance Measurement Mode
This bit forces the component into link reset then transmits the default
Intel IBIST pattern set of a fixed binary “1100” pattern continuously (depending
on implementation) on all Tx lanes until this bit is cleared. If the Intel IBIST
engine is used for CMM, then the standard initialization sequence is follow with
TS0, TS1 training set prior to entry into Intel IBIST.
0: Disable CMM
1: Enable CMM. This feature requires the Intel IBIST start bit to be set before the
mode is enabled.
ERRCNT: Error Counter [9:0]
Total number of errors encountered in this port. Errors are accumulated per lane.
If several errors occurred in one phit time then a binary encoded value of the
number of errors is added to the error count.
ERRLNNUM: Error Lane Number [3:0]
This points to the first lane that encountered an error. If more than one lane
reports an error in a cycle, the most significant lane number that reported the
error will be logged.
ERRSTAT: Port Error Status [1:0]
When Intel IBIST is started, status goes to 01 until first start delimiter is received
and then goes to 00 until the end or to10/11 as appropriate.
00: No error.
01: Did not receive first start delimiter.
10: Transmission error (first error).
11: Reserved.
AUTOINVSWPEN: Auto-inversion sweep enable
This bit enable the inversion shift register to continuously rotate the pattern in
the FIBTXSHFT and FIBRXSHFT registers. These registers enable the inversion
pattern to the lane at the bit position indicated by a logic 1.
0: Disable Auto-inversion
1: Enable Auto-inversion
STOPONERR: Stop Intel IBIST on Error
0: Do not stop on error, only update error counter
1: Stop on error
LOOPCON: Loop forever
0: No looping
1: Loop forever
IBDONE: Intel IBIST done flag
0: Not done
1: Done
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Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet