QG5000XSL9TH Datasheet, PDF (79/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.8.1.5
HDR - Header Type Register
This register identifies the header layout of the configuration space.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
0, 2-3, 8, 9
0
0Eh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
0Eh
Intel 5000Z Chipset
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
4-7
0
0Eh
Intel 5000P Chipset
16
0, 2
0Eh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
17
0
0Eh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
21
0
0Eh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
22
0
0Eh
Intel 5000P Chipset
Bit Attr Default
Description
7
RO
if
Multi-function Device.
(DEV16) _{Selects whether this is a multi-function device, that may have alternative}
{1h} _{configuration layouts. This bit is hardwired to ‘0’ for devices for the MCH with the}
else exception of device 16 fn 0-2, which it is set to ‘1’.
{0h}
endif
6:0 RO
if
Configuration Layout.
(DEV2-7) This field identifies the format of the configuration header layout for a PCI-to-PCI
{01h} _{bridge from bytes 10h through 3Fh.}
else
{00h}
endif
For PCI Express Devices 2,3,4,5,6,7 default is 01h, indicating “PCI to PCI Bridge”
For all other Devices: 0,8,9,16,17,21,22 default is 00h, indicating a conventional
type 00h PCI header
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
79